001
002
003
004
005
006
007
008
009
010
011
012
013
014
015
016
017
018
019
020
021
022
023
024
025
026
027
028
029
030
031
032
033
034
035
036
037
038
039
040
041
042
043
044
045
046
047
048
049
050
051
052
053
054
055
056
057
058
059
060
061
062
063
064
065
066
067
068
069
070
071
072
073
074
075
076
077
078

--**********************************************************************************
--*                                                                                *
--*                           Digital Clock peripheral logic                       *
--*                                                         Device : XC9536-PC44   *
--*                                                         Author : Seiichi Inoue *
--**********************************************************************************
library IEEE;                                         -- Library declaration
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clock2 is
    Port ( S,R : in std_logic_vector(1 downto 0);     -- SR-FF INPUT
           Q : out std_logic_vector(1 downto 0);      -- SR-FF OUTPUT
           CLK_10M : in std_logic;                    -- 1/200000 counter INPUT
           CLK_50 : out std_logic;                    -- 1/200000 counter OUTPUT
           A,B,C : in std_logic;                      -- 3-8 Decoder INPUT
           DEC : out std_logic_vector(7 downto 0));   -- 3-8 Decoder OUTPUT
  attribute pin_assign : string;                      -- Pin assign
  attribute pin_assign of S : signal is "6,2";
  attribute pin_assign of R : signal is "4,44";
  attribute pin_assign of Q : signal is "42,40";
  attribute pin_assign of CLK_10M : signal is "7";
  attribute pin_assign of CLK_50 : signal is "39";
  attribute pin_assign of A : signal is "37";
  attribute pin_assign of B : signal is "35";
  attribute pin_assign of C : signal is "33";
  attribute pin_assign of DEC : signal is "27,25,28,26,22,20,18,24";
end clock2;

architecture clock2_arch of clock2 is
  signal SI,RI,QI,QRI : std_logic_vector(1 downto 0); -- SR-FF signals
  signal Q100K : std_logic_vector(16 downto 0);       -- 1/100000 counter
  signal QCLK : std_logic_vector(0 downto 0);         -- 1/2 counter
  signal IN_DATA : std_logic_vector(2 downto 0);      -- 3-8 Decoder signals

begin
-- ** SR-FF **
  Q <= QI;                                            -- Set OUTPUT
  QI <= S nand SI;                                    -- Make NAND
  QRI <= R nand RI;                                   -- Make NAND
  SI <= QRI;                                          -- Connect QRI and SI
  RI <= QI;                                           -- Connect QI and RI

-- ** 1/200000 counter **
  CLK_50 <= QCLK(0);                                  -- Set OUTPUT
  process( CLK_10M ) begin
    if CLK_10M='1' and CLK_10M'event then             -- Clock rising edge ?
      if Q100K=99999 then                             -- Count = 100000 ?
         Q100K <= "00000000000000000";                -- YES. Clear counter
         QCLK <= QCLK + '1';                          -- Set 1/200000 counter
      else                                            -- No.
         Q100K <= Q100K + '1';                        -- Count-up
      end if;
    end if;
  end process;

-- ** 3-8 Decoder **
  IN_DATA <= C & B & A;                               -- Binding vector
  process( IN_DATA ) begin
    case IN_DATA is                                   -- Decode with input data
      when "000" => DEC <= "11111110";
      when "001" => DEC <= "11111101";
      when "010" => DEC <= "11111011";
      when "011" => DEC <= "11110111";
      when "100" => DEC <= "11101111";
      when "101" => DEC <= "11011111";
      when "110" => DEC <= "10111111";
      when "111" => DEC <= "01111111";
      when others => DEC <= "XXXXXXXX";               -- Illegal condition
    end case;
  end process;

end clock2_arch;

--**********************************************************************************
--*                       end of Digital Clock peripheral logic                    *
--**********************************************************************************