XACT: version D.19 Xilinx Inc.
Fitter Report
Design Name: selector1 Date: 7-21-2000, 10:07PM
Device Used: XC9536-15-PC44
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
4 /36 ( 11%) 16 /180 ( 8%) 0 /36 ( 0%) 22 /34 ( 64%) 20 /72 ( 27%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 18 18 | I/O : 22 6
Output : 4 4 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 2
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 22 22
MACROCELL RESOURCES:
Total Macrocells Available 36
Registered Macrocells 0
Non-registered Macrocell driving I/O 4
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 4 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 4 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
q<0> 4 6 FB1_2 STD FAST 3 I/O O
q<1> 4 6 FB1_11 STD FAST 13 I/O O
q<2> 4 6 FB2_2 STD FAST 44 I/O O
q<3> 4 6 FB2_11 STD FAST 34 I/O O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
a<0> FB1_10 12 I/O I
a<1> FB2_12 33 I/O I
a<2> FB2_13 29 I/O I
a<3> FB2_4 43 I/O I
b<0> FB2_9 36 I/O I
b<1> FB2_8 37 I/O I
b<2> FB2_14 28 I/O I
b<3> FB1_14 19 I/O I
c<0> FB2_10 35 I/O I
c<1> FB2_7 38 I/O I
c<2> FB1_4 4 I/O I
c<3> FB2_15 27 I/O I
d<0> FB1_6 8 I/O I
d<1> FB1_12 14 I/O I
d<2> FB1_13 18 I/O I
d<3> FB1_15 20 I/O I
sel<0> FB1_8 9 I/O I
sel<1> FB1_9 11 I/O I
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 2 10 10 8 2/0 17
FB2 2 10 10 8 2/0 17
---- ----- ----- -----
4 16 4/0 34
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 10/26
Number of signals used by logic mapping into function block: 10
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 2 I/O
q<0> 4 0 0 1 FB1_2 STD 3 I/O O
(unused) 0 0 0 5 FB1_3 5 GCK/I/O
(unused) 0 0 0 5 FB1_4 4 I/O I
(unused) 0 0 0 5 FB1_5 6 GCK/I/O
(unused) 0 0 0 5 FB1_6 8 I/O I
(unused) 0 0 0 5 FB1_7 7 GCK/I/O
(unused) 0 0 0 5 FB1_8 9 I/O I
(unused) 0 0 0 5 FB1_9 11 I/O I
(unused) 0 0 0 5 FB1_10 12 I/O I
q<1> 4 0 0 1 FB1_11 STD 13 I/O O
(unused) 0 0 0 5 FB1_12 14 I/O I
(unused) 0 0 0 5 FB1_13 18 I/O I
(unused) 0 0 0 5 FB1_14 19 I/O I
(unused) 0 0 0 5 FB1_15 20 I/O I
(unused) 0 0 0 5 FB1_16 22 I/O
(unused) 0 0 0 5 FB1_17 24 I/O
(unused) 0 0 0 5 FB1_18 (b)
Signals Used by Logic in Function Block
1: "a<0>" 5: "c<0>" 8: "d<1>"
2: "a<1>" 6: "c<1>" 9: "sel<0>"
3: "b<0>" 7: "d<0>" 10: "sel<1>"
4: "b<1>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
q<0> X.X.X.X.XX.............................. 6 6
q<1> .X.X.X.XXX.............................. 6 6
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 10/26
Number of signals used by logic mapping into function block: 10
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 1 I/O
q<2> 4 0 0 1 FB2_2 STD 44 I/O O
(unused) 0 0 0 5 FB2_3 42 GTS/I/O
(unused) 0 0 0 5 FB2_4 43 I/O I
(unused) 0 0 0 5 FB2_5 40 GTS/I/O
(unused) 0 0 0 5 FB2_6 39 GSR/I/O
(unused) 0 0 0 5 FB2_7 38 I/O I
(unused) 0 0 0 5 FB2_8 37 I/O I
(unused) 0 0 0 5 FB2_9 36 I/O I
(unused) 0 0 0 5 FB2_10 35 I/O I
q<3> 4 0 0 1 FB2_11 STD 34 I/O O
(unused) 0 0 0 5 FB2_12 33 I/O I
(unused) 0 0 0 5 FB2_13 29 I/O I
(unused) 0 0 0 5 FB2_14 28 I/O I
(unused) 0 0 0 5 FB2_15 27 I/O I
(unused) 0 0 0 5 FB2_16 26 I/O
(unused) 0 0 0 5 FB2_17 25 I/O
(unused) 0 0 0 5 FB2_18 (b)
Signals Used by Logic in Function Block
1: "a<2>" 5: "c<2>" 8: "d<3>"
2: "a<3>" 6: "c<3>" 9: "sel<0>"
3: "b<2>" 7: "d<2>" 10: "sel<1>"
4: "b<3>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
q<2> X.X.X.X.XX.............................. 6 6
q<3> .X.X.X.XXX.............................. 6 6
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
"q<2>" = "sel<0>" * "sel<1>" * "d<2>"
+ "sel<0>" * /"sel<1>" * "b<2>"
+ /"sel<0>" * "sel<1>" * "c<2>"
+ /"sel<0>" * /"sel<1>" * "a<2>"
"q<3>" = "sel<0>" * "sel<1>" * "d<3>"
+ "sel<0>" * /"sel<1>" * "b<3>"
+ /"sel<0>" * "sel<1>" * "c<3>"
+ /"sel<0>" * /"sel<1>" * "a<3>"
"q<0>" = "sel<0>" * "sel<1>" * "d<0>"
+ "sel<0>" * /"sel<1>" * "b<0>"
+ /"sel<0>" * "sel<1>" * "c<0>"
+ /"sel<0>" * /"sel<1>" * "a<0>"
"q<1>" = "sel<0>" * "sel<1>" * "d<1>"
+ "sel<0>" * /"sel<1>" * "b<1>"
+ /"sel<0>" * "sel<1>" * "c<1>"
+ /"sel<0>" * /"sel<1>" * "a<1>"
**************************** Device Pin Out ****************************
Device : XC9536-15-PC44
c q q a
T T < < T T < < T V T
I I 2 0 I I 2 3 I C I
E E > > E E > > E C E
--------------------------------
/6 5 4 3 2 1 44 43 42 41 40 \
TIE | 7 39 | TIE
d<0> | 8 38 | c<1>
sel<0> | 9 37 | b<1>
GND | 10 36 | b<0>
sel<1> | 11 XC9536-15-PC44 35 | c<0>
a<0> | 12 34 | q<3>
q<1> | 13 33 | a<1>
d<1> | 14 32 | VCC
TDI | 15 31 | GND
TMS | 16 30 | TDO
TCK | 17 29 | a<2>
\ 18 19 20 21 22 23 24 25 26 27 28 /
--------------------------------
d b d V T G T T T c b
< < < C I N I I I < <
2 3 3 C E D E E E 3 2
> > > > >
Legend : NC = Not Connected, unbonded pin
TIE = Tie pin to GND or board trace driven to valid logic level
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : XC9536-15-PC44
Use Timing Constraints : ON
Ignore Assignments In Design File : OFF
Create Programmable Ground Pins : OFF
Use Advanced Fitting : ON
Use Local Feedback : ON
Use Pin Feedback : ON
Default Power Setting : STD
Default Output Slew Rate : FAST
Guide File Used : NONE
Multi Level Logic Optimization : ON
Timing Optimization : ON
Power/Slew Optimization : OFF
High Fitting Effort : ON
Automatic Wire-ANDing : ON
Xor Synthesis : ON
D/T Synthesis : ON
Use Boolean Minimization : ON
Global Clock(GCK) Optimization : OFF
Global Set/Reset(GSR) Optimization : OFF
Global Output Enable(GTS) Optimization : OFF
Collapsing pterm limit : 25
Collapsing input limit : 36 |
