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045 | --******************************************************************************
--* *
--* 5 Binary Counter with Count Enable *
--* Device : XC9536-PC44 *
--* Author : Seiichi Inoue *
--******************************************************************************
library ieee; -- Defines std_logic types
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Counter5 is
port ( CLK,CLEAR,CE : in std_logic; -- Defines ports
Q5 : out std_logic_vector(2 downto 0));
attribute pin_assign : string; -- Pin Assign
attribute pin_assign of CE : signal is "1";
attribute pin_assign of Q5 : signal is "13,12,11";
attribute bufg: string;
attribute bufg of CLK : signal is "CLK";
attribute bufg of CLEAR : signal is "SR";
end Counter5;
architecture Counter5_ARCH of Counter5 is
signal Q5_IN : std_logic_vector(2 downto 0); -- Defines internal signals
begin
Q5 <= Q5_IN; -- Set output
process( CLEAR, CLK, CE ) begin
if CLEAR='0' then -- Clear counter ?
Q5_IN <= "000"; -- Yes. Clear counter
elsif CLK='1' and CLK'event then -- Clock rising edge ?
if CE='1' then -- Yes. Count Enable ?
if Q5_IN=4 then -- Yes. Count = 4 ?
Q5_IN <= "000"; -- Yes. Clear counter
else -- No
Q5_IN <= Q5_IN + '1'; -- Count-up
end if;
end if; -- Count Disable(Stop)
end if;
end process;
end Counter5_ARCH;
--******************************************************************************
--* end of 5 Binary Counter *
--****************************************************************************** |