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051 | --******************************************************************************
--* *
--* Synchronous Binary 4bits Up-Down Counter without Carry/Borrow *
--* Device : XC9536-PC44 *
--* Author : Seiichi Inoue *
--******************************************************************************
library ieee; -- Library declaration
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity UD_COUNTER1 is
port ( CLK,CLEAR,LOAD,CE,UP : in std_logic; -- INPUT and OUTPUT declaration
DIN : in std_logic_vector(3 downto 0);
Q : out std_logic_vector(3 downto 0));
attribute pin_assign : string; -- Pin assign
attribute pin_assign of CLK : signal is "1";
attribute pin_assign of CLEAR : signal is "2";
attribute pin_assign of LOAD : signal is "3";
attribute pin_assign of CE : signal is "4";
attribute pin_assign of UP : signal is "8";
attribute pin_assign of DIN : signal is "38,37,36,35";
attribute pin_assign of Q : signal is "14,13,12,11";
end UD_COUNTER1;
architecture UD_COUNTER_ARCH of UD_COUNTER1 is
signal Q_IN : std_logic_vector(3 downto 0); -- Internal counter signal
begin
Q <= Q_IN; -- Set output
process( CLEAR, CLK, LOAD, CE, UP ) begin
if CLEAR='1' then -- CLEAR = ON ?
Q_IN <= "0000"; -- Yes. Counter clear
elsif CLK='1' and CLK'event then -- Clock in ?
if LOAD='1' then -- Yes. LOAD = ON ?
Q_IN <= DIN; -- Set Input to Output
else -- LOAD = OFF
if CE='1' then -- Count Enable ?
if UP='1' then -- Yes. Up count ?
Q_IN <= Q_IN + '1'; -- Yes. Count-up
else -- Not count-up
Q_IN <= Q_IN - '1'; -- Count-down
end if;
end if; -- Not CE = 1
end if;
end if;
end process;
end UD_COUNTER_ARCH;
--******************************************************************************
--* end of Synchronous Binary 4bits Up-Down Counter *
--****************************************************************************** |