Source code and Explanation for 7 x 16 Latch Register ( Side B )

Source code and Explanation
for 7 x 16 Latch Register ( Side B )

--******************************************************************************
--*                                                                            *
--*                   7bits x 8rows Latch Register side B                      *
--*                                                     Device : XC9572-PC84   *
--*                                                     Author : Seiichi Inoue *
--******************************************************************************

library ieee;
use ieee.std_logic_1164.all;                         -- Defines std_logic types

entity Latch_B is
  port ( CLK : in std_logic;                         -- Defines Ports
         S : in std_logic_vector(3 downto 0);
         DIN : in std_logic_vector(6 downto 0);
         Q08, Q09, Q10, Q11 : out std_logic_vector(6 downto 0);
         Q12, Q13, Q14, Q15 : out std_logic_vector(6 downto 0));
  attribute pin_assign : string;                     -- Assigns Pins
  attribute pin_assign of S : signal is "68,70,72,74";
  attribute pin_assign of CLK : signal is "75";
  attribute pin_assign of DIN : signal is "51,53,54,56,58,62,66";
  attribute pin_assign of Q08 : signal is "43,44,41,39,40,37,35";
  attribute pin_assign of Q09 : signal is "55,52,50,47,48,45,46";
  attribute pin_assign of Q10 : signal is "76,71,69,67,65,63,61";
  attribute pin_assign of Q11 : signal is "77,79,80,81,82,83,84";
  attribute pin_assign of Q12 : signal is "1,2,3,4,5,6,7";
  attribute pin_assign of Q13 : signal is "9,10,11,13,12,14,15";
  attribute pin_assign of Q14 : signal is "17,18,19,20,21,23,24";
  attribute pin_assign of Q15 : signal is "25,26,31,32,34,33,36";
end Latch_B;

architecture Latch_arch of Latch_B is
  signal Q08_IN, Q09_IN, Q10_IN, Q11_IN : std_logic_vector(6 downto 0);
  signal Q12_IN, Q13_IN, Q14_IN, Q15_IN : std_logic_vector(6 downto 0);
  signal DUMY : std_logic_vector(6 downto 0);
begin
  Q08 <= Q08_IN;                                    -- Outputs Row 08
  Q09 <= Q09_IN;                                    -- Outputs Row 09
  Q10 <= Q10_IN;                                    -- Outputs Row 10
  Q11 <= Q11_IN;                                    -- Outputs Row 11
  Q12 <= Q12_IN;                                    -- Outputs Row 12
  Q13 <= Q13_IN;                                    -- Outputs Row 13
  Q14 <= Q14_IN;                                    -- Outputs Row 14
  Q15 <= Q15_IN;                                    -- Outputs Row 15
  process( S, CLK ) begin
    if CLK='0' and CLK'event then                   -- Clock falling edge ?
      case S is                                     -- Judgement with selector
        when "1000" => Q08_IN <= DIN;               -- Data latches for Row 08
        when "1001" => Q09_IN <= DIN;               -- Data latches for Row 09
        when "1010" => Q10_IN <= DIN;               -- Data latches for Row 10
        when "1011" => Q11_IN <= DIN;               -- Data latches for Row 11
        when "1100" => Q12_IN <= DIN;               -- Data latches for Row 12
        when "1101" => Q13_IN <= DIN;               -- Data latches for Row 13
        when "1110" => Q14_IN <= DIN;               -- Data latches for Row 14
        when "1111" => Q15_IN <= DIN;               -- Data latches for Row 15
        when others => DUMY <= DIN;                 -- Selector for side A
      end case;
    end if;
  end process;
end Latch_arch;

--******************************************************************************
--*                 end of 7bits x 8rows Latch Register side B                 *
--******************************************************************************

Explanation

Line #	Comment
009	The std_logic library is specified.
012 -016	The ports of the input/output are specified.
017 -028	The pins of the input/output are specified.
032 033	The register to use by the logical operation inside is defined. This is limitation on VHDL. The object which was specified as output (OUT) can not be used inside the entity. It is specified by the 7-bit vector like the output.
034	This is the dummy signal when the pattern of the Case sentence doesn't match(It specifies side A).
036 -043	It ties a counter for the inner calculation to the output counter.
045	"CLK='0' and CLK'event" is the description which detects that CLK changed into '0' from '1'.
046 -056	When detecting the falling edge of the clock, it generates the logic of the Case sentence. The input data are recorded to the latch registers which corresponds with the pattern of selection signal (S). In case of the pattern of side A, data are recorded to the dummy registers. Because "when others" can not be omitted, I am in this way.