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--******************************************************************************
--*                                                                            *
--*                   7bits x 8rows Latch Register side A                      *
--*                                                     Device : XC9572-PC84   *
--*                                                     Author : Seiichi Inoue *
--******************************************************************************

library ieee;
use ieee.std_logic_1164.all;                         -- Defines std_logic types

entity Latch_A is
  port ( CLK : in std_logic;                         -- Defines Ports
         S : in std_logic_vector(3 downto 0);
         DIN : in std_logic_vector(6 downto 0);
         Q00, Q01, Q02, Q03 : out std_logic_vector(6 downto 0);
         Q04, Q05, Q06, Q07 : out std_logic_vector(6 downto 0));
  attribute pin_assign : string;                     -- Assigns Pins
  attribute pin_assign of S : signal is "68,70,72,74";
  attribute pin_assign of CLK : signal is "75";
  attribute pin_assign of DIN : signal is "51,53,54,56,58,62,66";
  attribute pin_assign of Q00 : signal is "43,44,41,39,40,37,35";
  attribute pin_assign of Q01 : signal is "55,52,50,47,48,45,46";
  attribute pin_assign of Q02 : signal is "76,71,69,67,65,63,61";
  attribute pin_assign of Q03 : signal is "77,79,80,81,82,83,84";
  attribute pin_assign of Q04 : signal is "1,2,3,4,5,6,7";
  attribute pin_assign of Q05 : signal is "9,10,11,13,12,14,15";
  attribute pin_assign of Q06 : signal is "17,18,19,20,21,23,24";
  attribute pin_assign of Q07 : signal is "25,26,31,32,34,33,36";
end Latch_A;

architecture Latch_arch of Latch_A is
  signal Q00_IN, Q01_IN, Q02_IN, Q03_IN : std_logic_vector(6 downto 0);
  signal Q04_IN, Q05_IN, Q06_IN, Q07_IN : std_logic_vector(6 downto 0);
  signal DUMY : std_logic_vector(6 downto 0);
begin
  Q00 <= Q00_IN;                                    -- Outputs Row 00
  Q01 <= Q01_IN;                                    -- Outputs Row 01
  Q02 <= Q02_IN;                                    -- Outputs Row 02
  Q03 <= Q03_IN;                                    -- Outputs Row 03
  Q04 <= Q04_IN;                                    -- Outputs Row 04
  Q05 <= Q05_IN;                                    -- Outputs Row 05
  Q06 <= Q06_IN;                                    -- Outputs Row 06
  Q07 <= Q07_IN;                                    -- Outputs Row 07
  process( S, CLK ) begin
    if CLK='0' and CLK'event then                   -- Clock falling edge ?
      case S is                                     -- Judgement with selector
        when "0000" => Q00_IN <= DIN;               -- Data latches for Row 00
        when "0001" => Q01_IN <= DIN;               -- Data latches for Row 01
        when "0010" => Q02_IN <= DIN;               -- Data latches for Row 02
        when "0011" => Q03_IN <= DIN;               -- Data latches for Row 03
        when "0100" => Q04_IN <= DIN;               -- Data latches for Row 04
        when "0101" => Q05_IN <= DIN;               -- Data latches for Row 05
        when "0110" => Q06_IN <= DIN;               -- Data latches for Row 06
        when "0111" => Q07_IN <= DIN;               -- Data latches for Row 07
        when others => DUMY <= DIN;                 -- Selector for side B
      end case;
    end if;
  end process;
end Latch_arch;

--******************************************************************************
--*                 end of 7bits x 8rows Latch Register side A                 *
--******************************************************************************