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--******************************************************************************
--*                                                                            *
--*                              8 - 3 Encoder                                 *
--*                                                     Device : XC9536-PC44   *
--*                                                     Author : Seiichi Inoue *
--******************************************************************************

library ieee;                                    -- Defines std_logic types
use ieee.std_logic_1164.all;

entity Encoder1 is
  port ( A, B, C, D, E, F, G, H : in std_logic;  -- Defines ports
         Q : out std_logic_vector(2 downto 0);
         ERROR : out std_logic);
end Encoder1;

architecture Encoder1_arch of Encoder1 is
  signal IN_DATA : std_logic_vector(7 downto 0); -- Defines internal signals
begin
  IN_DATA <= H & G & F & E & D & C & B & A;      -- Binding vector
  process( IN_DATA ) begin
    ERROR <= '0';                                -- Clear error bit
    case IN_DATA is                              -- Encode with input data
      when "00000001" => Q <= "000";
      when "00000010" => Q <= "001";
      when "00000100" => Q <= "010";
      when "00001000" => Q <= "011";
      when "00010000" => Q <= "100";
      when "00100000" => Q <= "101";
      when "01000000" => Q <= "110";
      when "10000000" => Q <= "111";
      when others => ERROR <= '1';               -- Illegal condition
    end case;
  end process;
end Encoder1_arch;

--******************************************************************************
--*                             end of 3 - 8 Encoder                           *
--******************************************************************************