XACT: version D.19 Xilinx Inc.
Fitter Report
Design Name: decoder2 Date: 7-20-2000, 5:16PM
Device Used: XC9536-15-PC44
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
16 /36 ( 44%) 16 /180 ( 8%) 0 /36 ( 0%) 20 /34 ( 58%) 8 /72 ( 11%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 4 4 | I/O : 20 8
Output : 16 16 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 2
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 20 20
MACROCELL RESOURCES:
Total Macrocells Available 36
Registered Macrocells 0
Non-registered Macrocell driving I/O 16
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 16 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 16 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
q<0> 1 4 FB2_11 STD FAST 34 I/O O
q<10> 1 4 FB2_13 STD FAST 29 I/O O
q<11> 1 4 FB2_15 STD FAST 27 I/O O
q<12> 1 4 FB2_17 STD FAST 25 I/O O
q<13> 1 4 FB1_17 STD FAST 24 I/O O
q<14> 1 4 FB1_2 STD FAST 3 I/O O
q<15> 1 4 FB1_4 STD FAST 4 I/O O
q<1> 1 4 FB1_6 STD FAST 8 I/O O
q<2> 1 4 FB1_9 STD FAST 11 I/O O
q<3> 1 4 FB1_11 STD FAST 13 I/O O
q<4> 1 4 FB1_13 STD FAST 18 I/O O
q<5> 1 4 FB1_15 STD FAST 20 I/O O
q<6> 1 4 FB2_2 STD FAST 44 I/O O
q<7> 1 4 FB2_4 STD FAST 43 I/O O
q<8> 1 4 FB2_7 STD FAST 38 I/O O
q<9> 1 4 FB2_9 STD FAST 36 I/O O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
a FB1_10 12 I/O I
b FB1_8 9 I/O I
c FB2_10 35 I/O I
d FB2_8 37 I/O I
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 8 4 4 8 8/0 17
FB2 8 4 4 8 8/0 17
---- ----- ----- -----
16 16 16/0 34
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 4/32
Number of signals used by logic mapping into function block: 4
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 2 I/O
q<14> 1 0 0 4 FB1_2 STD 3 I/O O
(unused) 0 0 0 5 FB1_3 5 GCK/I/O
q<15> 1 0 0 4 FB1_4 STD 4 I/O O
(unused) 0 0 0 5 FB1_5 6 GCK/I/O
q<1> 1 0 0 4 FB1_6 STD 8 I/O O
(unused) 0 0 0 5 FB1_7 7 GCK/I/O
(unused) 0 0 0 5 FB1_8 9 I/O I
q<2> 1 0 0 4 FB1_9 STD 11 I/O O
(unused) 0 0 0 5 FB1_10 12 I/O I
q<3> 1 0 0 4 FB1_11 STD 13 I/O O
(unused) 0 0 0 5 FB1_12 14 I/O
q<4> 1 0 0 4 FB1_13 STD 18 I/O O
(unused) 0 0 0 5 FB1_14 19 I/O
q<5> 1 0 0 4 FB1_15 STD 20 I/O O
(unused) 0 0 0 5 FB1_16 22 I/O
q<13> 1 0 0 4 FB1_17 STD 24 I/O O
(unused) 0 0 0 5 FB1_18 (b)
Signals Used by Logic in Function Block
1: a 3: c 4: d
2: b
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
q<14> XXXX.................................... 4 4
q<15> XXXX.................................... 4 4
q<1> XXXX.................................... 4 4
q<2> XXXX.................................... 4 4
q<3> XXXX.................................... 4 4
q<4> XXXX.................................... 4 4
q<5> XXXX.................................... 4 4
q<13> XXXX.................................... 4 4
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 4/32
Number of signals used by logic mapping into function block: 4
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 1 I/O
q<6> 1 0 0 4 FB2_2 STD 44 I/O O
(unused) 0 0 0 5 FB2_3 42 GTS/I/O
q<7> 1 0 0 4 FB2_4 STD 43 I/O O
(unused) 0 0 0 5 FB2_5 40 GTS/I/O
(unused) 0 0 0 5 FB2_6 39 GSR/I/O
q<8> 1 0 0 4 FB2_7 STD 38 I/O O
(unused) 0 0 0 5 FB2_8 37 I/O I
q<9> 1 0 0 4 FB2_9 STD 36 I/O O
(unused) 0 0 0 5 FB2_10 35 I/O I
q<0> 1 0 0 4 FB2_11 STD 34 I/O O
(unused) 0 0 0 5 FB2_12 33 I/O
q<10> 1 0 0 4 FB2_13 STD 29 I/O O
(unused) 0 0 0 5 FB2_14 28 I/O
q<11> 1 0 0 4 FB2_15 STD 27 I/O O
(unused) 0 0 0 5 FB2_16 26 I/O
q<12> 1 0 0 4 FB2_17 STD 25 I/O O
(unused) 0 0 0 5 FB2_18 (b)
Signals Used by Logic in Function Block
1: a 3: c 4: d
2: b
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
q<6> XXXX.................................... 4 4
q<7> XXXX.................................... 4 4
q<8> XXXX.................................... 4 4
q<9> XXXX.................................... 4 4
q<0> XXXX.................................... 4 4
q<10> XXXX.................................... 4 4
q<11> XXXX.................................... 4 4
q<12> XXXX.................................... 4 4
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
"q<6>" = b * c * /a * /d
"q<7>" = b * c * a * /d
"q<8>" = /b * /c * /a * d
"q<9>" = /b * /c * a * d
"q<0>" = /b * /c * /a * /d
"q<10>" = b * /c * /a * d
"q<11>" = b * /c * a * d
"q<12>" = /b * c * /a * d
"q<13>" = /b * c * a * d
"q<14>" = b * c * /a * d
"q<15>" = b * c * a * d
"q<1>" = /b * /c * a * /d
"q<2>" = b * /c * /a * /d
"q<3>" = b * /c * a * /d
"q<4>" = /b * c * /a * /d
"q<5>" = /b * c * a * /d
**************************** Device Pin Out ****************************
Device : XC9536-15-PC44
q q
< < q q
T T 1 1 T T < < T V T
I I 5 4 I I 6 7 I C I
E E > > E E > > E C E
--------------------------------
/6 5 4 3 2 1 44 43 42 41 40 \
TIE | 7 39 | TIE
q<1> | 8 38 | q<8>
b | 9 37 | d
GND | 10 36 | q<9>
q<2> | 11 XC9536-15-PC44 35 | c
a | 12 34 | q<0>
q<3> | 13 33 | TIE
TIE | 14 32 | VCC
TDI | 15 31 | GND
TMS | 16 30 | TDO
TCK | 17 29 | q<10>
\ 18 19 20 21 22 23 24 25 26 27 28 /
--------------------------------
q T q V T G q q T q T
< I < C I N < < I < I
4 E 5 C E D 1 1 E 1 E
> > 3 2 1
> > >
Legend : NC = Not Connected, unbonded pin
TIE = Tie pin to GND or board trace driven to valid logic level
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : XC9536-15-PC44
Use Timing Constraints : ON
Ignore Assignments In Design File : OFF
Create Programmable Ground Pins : OFF
Use Advanced Fitting : ON
Use Local Feedback : ON
Use Pin Feedback : ON
Default Power Setting : STD
Default Output Slew Rate : FAST
Guide File Used : NONE
Multi Level Logic Optimization : ON
Timing Optimization : ON
Power/Slew Optimization : OFF
High Fitting Effort : ON
Automatic Wire-ANDing : ON
Xor Synthesis : ON
D/T Synthesis : ON
Use Boolean Minimization : ON
Global Clock(GCK) Optimization : OFF
Global Set/Reset(GSR) Optimization : OFF
Global Output Enable(GTS) Optimization : OFF
Collapsing pterm limit : 25
Collapsing input limit : 36 |
