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SFR explanation for PIC16F873(14)

ADRESH,ADRESL ( A/D Result Registers ) 1Eh, 9Eh
    A/D conversion result is loaded to these registers.
Two registers are combined and works as a 16 bits register.
The A/D module gives the flexibility to left or right justify the 10 bits result in the 10 bits result register.




ADCON0 ( A/D converter control register 0 ) 1Fh
    The A/D converter condition is controlled with this register.

The value in the parenthesis is in the condition immediately after the turning on.

ADCS1,ADCS0 : A/D conversion clock select bits
ADCS1ADCS0Clock
00Fosc/2
01Fosc/8
10Fosc/32
11RC
In case of RC, the clock is driven from an RC oscillator.

CHS2,CHS1,CHS0 : Analog channel select bits
CHS2CHS1CHS0Input channel
000Channel 0 ( RA0/AN0 )
001Channel 1 ( RA1/AN1 )
010Channel 2 ( RA2/AN2 )
011Channel 3 ( RA3/AN3 )
100Channel 4 ( RA5/AN4 )
101 Unimplemented
For PIC16F874/877
110
111



GO/DONE : A/D conversion status bit
1:A/D conversion in progress
0:A/D conversion not in progress ( This bit is automatically cleared by hardware )

ADON : A/D ON bit
1:A/D conversion module is operating
0:A/D conversion module is shutoff and operating current




ADCON1 ( A/D converter control register 1 ) 9Fh
The A/D converter condition is controlled with this register.

The value in the parenthesis is in the condition immediately after the turning on.

ADFM : A/D result format select
1:Right justified. 6 most significant bits of ADRESH are read as 0.
0:Left justified. 6 least significant bits of ADRESL are read as 0.

PCFG3,PCFG2,PCFG1,PCFG0 : A/D port configuration control bits
PCFG
3210
Port Remarks
AN4AN3AN2AN1AN0
0000AAAAA
0001AVREF+AAA
0010AAAAASame as 0000
0011AVREF+AAASame as 0001
0100DADAA
0101DVREF+DAA
0110DDDDD
0111DDDDDSame as 0110
1000AVREF+VREF-AA
1001AAAAASame as 0000
1010AVREF+AAASame as 0001
1011AVREF+VREF-AASame as 1000
1100AVREF+VREF-AASame as 1000
1101DVREF+VREF-AA
1110DDDDA
1111DVREF+VREF-DA
A: Analog port
D: Digital port
VREF+: High reference voltage
VREF-: Low reference voltage