Instruction set

RRF	Rotate Right f through Carry
Form	[label]RRFf, d ( label is omitable, shows SPACE code )
Operands	f : Register file addesss ( 00(00h) to 127(7Fh) ) d : Destination select ( 0 or 1 )
Operation	It moves the contents of the f register to the 1-bit right including the carry bit. d = 0 : store result in W d = 1 : store result in f
Flag	It sets the least significant bit of the f register to C.
Instruction cycles	1 cycle

SLEEP	Go into stanby mode
Form	[label]SLEEP ( label is omitable, shows SPACE code )
Operands	None
Operation	It stops a clock generator and it makes a processor a standby mode. It resets a watchdog timer. When using the prescaler for the watchdog timer, it resets the prescaler, too.
Flag	It sets 1 to TO and it sets 0 to the PD.
Instruction cycles	1 cycle

SUBLW	Subtract W from literal
Form	[label]SUBLWk ( label is omitable, shows SPACE code )
Operands	k : literal field ( 00(00h) to 255(FFh) )
Operation	It executes the subtraction of the contents of the W register from the literal data. In the actual calculation, it changes the content of the W register by the 2's complement and it adds with the literal data. (EX)
Flag	C=1, Z=0 ( Result is positive ) C=1, Z=1 ( Result is zero ) C=0, Z=0 ( Result is negative )
Instruction cycles	1 cycle

SUBWF	Subtract W from f
Form	[label]SUBWFf, d ( label is omitable, shows SPACE code )
Operands	f : Register file addesss ( 00(00h) to 127(7Fh) ) d : Destination select ( 0 or 1 )
Operation	It executes the subtraction of the contents of the W register from the f register. d = 0 : store result in W d = 1 : store result in f In the actual calculation, it changes the content of the W register by the 2's complement and it adds with the contents of the f register. (EX)
Flag	C=1, Z=0 ( Result is positive ) C=1, Z=1 ( Result is zero ) C=0, Z=0 ( Result is negative )
Instruction cycles	1 cycle

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