Instruction set
ADDLW | Add W and f |
Form |
[label]ADDLWk
( label is omitable, shows SPACE code ) |
Operands | k : literal field ( 00(00h) to 255(FFh) ) |
Operation |
It executes the addition of the literal data and the contents of the W register.
(EX) | |
Flag |
When the byte overflows, it sets 1 to the C flag.
When 4 bits of lower part overflow, it sets 1 to the DC flag.
When the result is 0, it sets 1 to the Z flag.
In the case except the above, it sets 0 to C, DC and Z. |
Instruction
cycles | 1 cycle |
ADDWF | AND W with f |
Form |
[label]ADDWFf, d
( label is omitable, shows SPACE code ) |
Operands |
f : Register file addesss ( 00(00h) to 127(7Fh) )
d : Destination select ( 0 or 1 ) |
Operation |
It executes the addition of the contents of the f register and the W register.
d = 0 : store result in W
d = 1 : store result in f
(EX) | |
Flag |
When the byte overflows, it sets 1 to the C flag.
When 4 bits of lower part overflow, it sets 1 to the DC flag.
When the result is 0, it sets 1 to the Z flag.
In the case except the above, it sets 0 to C, DC and Z. |
Instruction
cycles | 1 cycle |
ANDLW | AND literal with W |
Form |
[label]ADDLWk
( label is omitable, shows SPACE code ) |
Operands | k : literal field ( 00(00h) to 255(FFh) ) |
Operation |
It executes the logic AND operation of the literal data and the contents of the W register.
(EX) | |
Flag |
When the result is 0, it sets 1 to the Z flag.
When the result is not 0, it sets 0 to the Z flag. |
Instruction
cycles | 1 cycle |
ANDWF | AND W with f |
Form |
[label]ANDWFf, d
( label is omitable, shows SPACE code ) |
Operands |
f : Register file addesss ( 00(00h) to 127(7Fh) )
d : Destination select ( 0 or 1 ) |
Operation |
It executes the logic AND operation of the contents of the f register and the W register.
d = 0 : store result in W
d = 1 : store result in f
(EX) | |
Flag |
When the result is 0, it sets 1 to the Z flag.
When the result is not 0, it sets 0 to the Z flag. |
Instruction
cycles | 1 cycle |
Next instructions
|