XACT: version D.20 Xilinx Inc.
Fitter Report
Design Name: clock2 Date: 2-22-2001, 8:51PM
Device Used: XC9536-15-PC44
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
30 /36 ( 83%) 60 /180 ( 33%) 18 /36 ( 50%) 19 /34 ( 55%) 46 /72 ( 63%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 8 8 | I/O : 14 14
Output : 11 11 | GCK/IO : 2 1
Bidirectional : 0 0 | GTS/IO : 2 0
GCK : 0 0 | GSR/IO : 1 0
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 19 19
MACROCELL RESOURCES:
Total Macrocells Available 36
Registered Macrocells 18
Non-registered Macrocell driving I/O 10
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 30 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 30 macrocells used (MC).
End of Resource Summary
**************************** Errors and Warnings *************************
WARNING:nd300 - The signal(s) 'N310, N317' are in combinational feedback
loops.
These signals may cause hazards/glitches. Logic should include hazard
reduction circuitry to avoid hazards/glitches. Apply the NOREDUCE parameter
to the hazard reduction circuitry.
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
N310 2 3 FB1_18 STD (b) (b)
N317 2 3 FB1_14 STD 19 I/O (b)
clk_50 2 18 FB2_6 STD FAST 39 GSR/I/O O
dec<0> 1 3 FB1_17 STD FAST 24 I/O O
dec<1> 1 3 FB1_13 STD FAST 18 I/O O
dec<2> 1 3 FB1_15 STD FAST 20 I/O O
dec<3> 1 3 FB1_16 STD FAST 22 I/O O
dec<4> 1 3 FB2_16 STD FAST 26 I/O O
dec<5> 1 3 FB2_14 STD FAST 28 I/O O
dec<6> 1 3 FB2_17 STD FAST 25 I/O O
dec<7> 1 3 FB2_15 STD FAST 27 I/O O
q100k_0 2 2 FB1_12 STD 14 I/O (b)
q100k_1 2 2 FB1_11 STD 13 I/O (b)
q100k_10 3 18 FB2_13 STD 29 I/O (b)
q100k_11 2 12 FB1_10 STD 12 I/O (b)
q100k_12 2 13 FB2_8 STD 37 I/O I
q100k_13 2 14 FB2_7 STD 38 I/O (b)
q100k_14 2 15 FB2_4 STD 43 I/O (b)
q100k_15 3 18 FB2_12 STD 33 I/O I
q100k_16 3 18 FB2_11 STD 34 I/O (b)
q100k_2 2 3 FB1_9 STD 11 I/O (b)
q100k_3 2 4 FB1_8 STD 9 I/O (b)
q100k_4 2 5 FB1_7 STD 7 GCK/I/O I
q100k_5 7 18 FB2_18 STD (b) (b)
q100k_6 2 7 FB1_6 STD 8 I/O (b)
q100k_7 3 18 FB2_10 STD 35 I/O I
q100k_8 2 9 FB1_5 STD 6 GCK/I/O I
q100k_9 3 18 FB2_9 STD 36 I/O (b)
q<0> 1 2 FB2_5 STD FAST 40 GTS/I/O O
q<1> 1 2 FB2_3 STD FAST 42 GTS/I/O O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
a FB2_8 37 I/O I
b FB2_10 35 I/O I
c FB2_12 33 I/O I
clk_10m FB1_7 7 GCK/I/O I
r<0> FB2_2 44 I/O I
r<1> FB1_4 4 I/O I
s<0> FB1_1 2 I/O I
s<1> FB1_5 6 GCK/I/O I
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 14 21 21 24 4/0 17
FB2 16 25 25 36 7/0 17
---- ----- ----- -----
30 60 11/0 34
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 21/15
Number of signals used by logic mapping into function block: 21
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 2 I/O I
(unused) 0 0 0 5 FB1_2 3 I/O
(unused) 0 0 0 5 FB1_3 5 GCK/I/O
(unused) 0 0 0 5 FB1_4 4 I/O I
q100k_8 2 0 0 3 FB1_5 STD 6 GCK/I/O I
q100k_6 2 0 0 3 FB1_6 STD 8 I/O (b)
q100k_4 2 0 0 3 FB1_7 STD 7 GCK/I/O I
q100k_3 2 0 0 3 FB1_8 STD 9 I/O (b)
q100k_2 2 0 0 3 FB1_9 STD 11 I/O (b)
q100k_11 2 0 0 3 FB1_10 STD 12 I/O (b)
q100k_1 2 0 0 3 FB1_11 STD 13 I/O (b)
q100k_0 2 0 0 3 FB1_12 STD 14 I/O (b)
dec<1> 1 0 0 4 FB1_13 STD 18 I/O O
N317 2 0 0 3 FB1_14 STD 19 I/O (b)
dec<2> 1 0 0 4 FB1_15 STD 20 I/O O
dec<3> 1 0 0 4 FB1_16 STD 22 I/O O
dec<0> 1 0 0 4 FB1_17 STD 24 I/O O
N310 2 0 0 3 FB1_18 STD (b) (b)
Signals Used by Logic in Function Block
1: N310 8: q100k_1 15: q100k_7
2: N317 9: q100k_10 16: q100k_8
3: a 10: q100k_2 17: q100k_9
4: b 11: q100k_3 18: "r<0>"
5: c 12: q100k_4 19: "r<1>"
6: clk_10m 13: q100k_5 20: "s<0>"
7: q100k_0 14: q100k_6 21: "s<1>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
q100k_8 .....XXX.XXXXXX......................... 9 9
q100k_6 .....XXX.XXXX........................... 7 7
q100k_4 .....XXX.XX............................. 5 5
q100k_3 .....XXX.X.............................. 4 4
q100k_2 .....XXX................................ 3 3
q100k_11 .....XXXXXXXXXXXX....................... 12 12
q100k_1 .....XX................................. 2 2
q100k_0 .....XX................................. 2 2
dec<1> ..XXX................................... 3 3
N317 .X................X.X................... 3 3
dec<2> ..XXX................................... 3 3
dec<3> ..XXX................................... 3 3
dec<0> ..XXX................................... 3 3
N310 X................X.X.................... 3 3
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 25/11
Number of signals used by logic mapping into function block: 25
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 1 I/O
(unused) 0 0 0 5 FB2_2 44 I/O I
q<1> 1 0 0 4 FB2_3 STD 42 GTS/I/O O
q100k_14 2 0 0 3 FB2_4 STD 43 I/O (b)
q<0> 1 0 0 4 FB2_5 STD 40 GTS/I/O O
clk_50 2 0 0 3 FB2_6 STD 39 GSR/I/O O
q100k_13 2 0 0 3 FB2_7 STD 38 I/O (b)
q100k_12 2 0 0 3 FB2_8 STD 37 I/O I
q100k_9 3 0 0 2 FB2_9 STD 36 I/O (b)
q100k_7 3 0 0 2 FB2_10 STD 35 I/O I
q100k_16 3 0 0 2 FB2_11 STD 34 I/O (b)
q100k_15 3 0 0 2 FB2_12 STD 33 I/O I
q100k_10 3 0 0 2 FB2_13 STD 29 I/O (b)
dec<5> 1 0 0 4 FB2_14 STD 28 I/O O
dec<7> 1 0 0 4 FB2_15 STD 27 I/O O
dec<4> 1 0 0 4 FB2_16 STD 26 I/O O
dec<6> 1 0 \/2 2 FB2_17 STD 25 I/O O
q100k_5 7 2<- 0 0 FB2_18 STD (b) (b)
Signals Used by Logic in Function Block
1: N310 10: q100k_11 18: q100k_4
2: N317 11: q100k_12 19: q100k_5
3: a 12: q100k_13 20: q100k_6
4: b 13: q100k_14 21: q100k_7
5: c 14: q100k_15 22: q100k_8
6: clk_10m 15: q100k_16 23: q100k_9
7: q100k_0 16: q100k_2 24: "s<0>"
8: q100k_1 17: q100k_3 25: "s<1>"
9: q100k_10
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
q<1> .X......................X............... 2 2
q100k_14 .....XXXXXXX...XXXXXXXX................. 15 15
q<0> X......................X................ 2 2
clk_50 .....XXXXXXXXXXXXXXXXXX................. 18 18
q100k_13 .....XXXXXX....XXXXXXXX................. 14 14
q100k_12 .....XXXXX.....XXXXXXXX................. 13 13
q100k_9 .....XXXXXXXXXXXXXXXXXX................. 18 18
q100k_7 .....XXXXXXXXXXXXXXXXXX................. 18 18
q100k_16 .....XXXXXXXXXXXXXXXXXX................. 18 18
q100k_15 .....XXXXXXXXXXXXXXXXXX................. 18 18
q100k_10 .....XXXXXXXXXXXXXXXXXX................. 18 18
dec<5> ..XXX................................... 3 3
dec<7> ..XXX................................... 3 3
dec<4> ..XXX................................... 3 3
dec<6> ..XXX................................... 3 3
q100k_5 .....XXX@@@@@@@XX@@@@@@................. 18 5
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
Eliminating
**************************** Device Pin Out ****************************
Device : XC9536-15-PC44
s r s r q q
< T < T < T < T < V <
1 I 1 I 0 I 0 I 1 C 0
> E > E > E > E > C >
--------------------------------
/6 5 4 3 2 1 44 43 42 41 40 \
clk_10m | 7 39 | clk_50
TIE | 8 38 | TIE
TIE | 9 37 | a
GND | 10 36 | TIE
TIE | 11 XC9536-15-PC44 35 | b
TIE | 12 34 | TIE
TIE | 13 33 | c
TIE | 14 32 | VCC
TDI | 15 31 | GND
TMS | 16 30 | TDO
TCK | 17 29 | TIE
\ 18 19 20 21 22 23 24 25 26 27 28 /
--------------------------------
d T d V d G d d d d d
e I e C e N e e e e e
c E c C c D c c c c c
< < < < < < < <
1 2 3 0 6 4 7 5
> > > > > > > >
Legend : NC = Not Connected, unbonded pin
TIE = Tie pin to GND or board trace driven to valid logic level
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : XC9536-15-PC44
Use Timing Constraints : ON
Ignore Assignments In Design File : OFF
Create Programmable Ground Pins : OFF
Use Advanced Fitting : ON
Use Local Feedback : ON
Use Pin Feedback : ON
Default Power Setting : STD
Default Output Slew Rate : FAST
Guide File Used : NONE
Multi Level Logic Optimization : ON
Timing Optimization : ON
Power/Slew Optimization : OFF
High Fitting Effort : ON
Automatic Wire-ANDing : ON
Xor Synthesis : ON
D/T Synthesis : ON
Use Boolean Minimization : ON
Global Clock(GCK) Optimization : OFF
Global Set/Reset(GSR) Optimization : OFF
Global Output Enable(GTS) Optimization : OFF
Collapsing pterm limit : 25
Collapsing input limit : 36 |
