XACT: version D.19 Xilinx Inc.
Fitter Report
Design Name: led_shifter Date: 8- 7-2000, 7:09PM
Device Used: XC9536-15-PC44
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
28 /36 ( 77%) 127 /180 ( 70%) 28 /36 ( 77%) 27 /34 ( 79%) 20 /72 ( 27%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 2 2 | I/O : 21 7
Output : 20 20 | GCK/IO : 3 0
Bidirectional : 5 5 | GTS/IO : 2 0
GCK : 0 0 | GSR/IO : 1 0
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 27 27
MACROCELL RESOURCES:
Total Macrocells Available 36
Registered Macrocells 28
Non-registered Macrocell driving I/O 0
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 28 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 28 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
counter_0 2 4 FB2_18 STD (b) (b)
counter_1 2 2 FB2_17 STD 25 I/O (b)
counter_2 3 4 FB1_18 STD (b) (b)
qa<0> 5 6 FB2_6 STD FAST 39 GSR/I/O I/O
qa<1> 5 6 FB2_8 STD FAST 37 I/O I/O
qa<2> 4 5 FB2_7 STD FAST 38 I/O I/O
qa<3> 5 6 FB2_10 STD FAST 35 I/O I/O
qa<4> 5 6 FB2_9 STD FAST 36 I/O I/O
qb<0> 5 6 FB2_2 STD FAST 44 I/O O
qb<1> 5 6 FB2_1 STD FAST 1 I/O O
qb<2> 4 5 FB2_3 STD FAST 42 GTS/I/O O
qb<3> 5 6 FB2_4 STD FAST 43 I/O O
qb<4> 5 6 FB2_5 STD FAST 40 GTS/I/O O
qc<0> 5 6 FB1_5 STD FAST 6 GCK/I/O O
qc<1> 5 6 FB1_6 STD FAST 8 I/O O
qc<2> 4 5 FB1_4 STD FAST 4 I/O O
qc<3> 5 6 FB1_3 STD FAST 5 GCK/I/O O
qc<4> 5 6 FB1_1 STD FAST 2 I/O O
qd<0> 5 6 FB1_7 STD FAST 7 GCK/I/O O
qd<1> 5 6 FB1_8 STD FAST 9 I/O O
qd<2> 4 5 FB1_9 STD FAST 11 I/O O
qd<3> 5 6 FB1_10 STD FAST 12 I/O O
qd<4> 5 6 FB1_11 STD FAST 13 I/O O
qe<0> 5 6 FB1_14 STD FAST 19 I/O O
qe<1> 5 6 FB1_13 STD FAST 18 I/O O
qe<2> 4 5 FB1_15 STD FAST 20 I/O O
qe<3> 5 6 FB1_16 STD FAST 22 I/O O
qe<4> 5 6 FB1_17 STD FAST 24 I/O O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
clk FB2_13 29 I/O I
right FB2_14 28 I/O I
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 16 10 10 75 15/0 17
FB2 12 10 10 52 5/5 17
---- ----- ----- -----
28 127 20/5 34
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 10/26
Number of signals used by logic mapping into function block: 10
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
qc<4> 5 0 0 0 FB1_1 STD 2 I/O O
(unused) 0 0 0 5 FB1_2 3 I/O
qc<3> 5 0 0 0 FB1_3 STD 5 GCK/I/O O
qc<2> 4 0 0 1 FB1_4 STD 4 I/O O
qc<0> 5 0 0 0 FB1_5 STD 6 GCK/I/O O
qc<1> 5 0 0 0 FB1_6 STD 8 I/O O
qd<0> 5 0 0 0 FB1_7 STD 7 GCK/I/O O
qd<1> 5 0 0 0 FB1_8 STD 9 I/O O
qd<2> 4 0 0 1 FB1_9 STD 11 I/O O
qd<3> 5 0 0 0 FB1_10 STD 12 I/O O
qd<4> 5 0 0 0 FB1_11 STD 13 I/O O
(unused) 0 0 0 5 FB1_12 14 I/O
qe<1> 5 0 0 0 FB1_13 STD 18 I/O O
qe<0> 5 0 0 0 FB1_14 STD 19 I/O O
qe<2> 4 0 0 1 FB1_15 STD 20 I/O O
qe<3> 5 0 0 0 FB1_16 STD 22 I/O O
qe<4> 5 0 0 0 FB1_17 STD 24 I/O O
counter_2 3 0 0 2 FB1_18 STD (b) (b)
Signals Used by Logic in Function Block
1: clk 5: "qa<0>" 8: "qa<3>"
2: counter_0 6: "qa<1>" 9: "qa<4>"
3: counter_1 7: "qa<2>" 10: right
4: counter_2
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
qc<4> XXXX....XX.............................. 6 6
qc<3> XXXX...X.X.............................. 6 6
qc<2> XXXX..X................................. 5 5
qc<0> XXXXX....X.............................. 6 6
qc<1> XXXX.X...X.............................. 6 6
qd<0> XXXXX....X.............................. 6 6
qd<1> XXXX.X...X.............................. 6 6
qd<2> XXXX..X................................. 5 5
qd<3> XXXX...X.X.............................. 6 6
qd<4> XXXX....XX.............................. 6 6
qe<1> XXXX.X...X.............................. 6 6
qe<0> XXXXX....X.............................. 6 6
qe<2> XXXX..X................................. 5 5
qe<3> XXXX...X.X.............................. 6 6
qe<4> XXXX....XX.............................. 6 6
counter_2 XXXX.................................... 4 4
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 10/26
Number of signals used by logic mapping into function block: 10
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
qb<1> 5 0 0 0 FB2_1 STD 1 I/O O
qb<0> 5 0 0 0 FB2_2 STD 44 I/O O
qb<2> 4 0 0 1 FB2_3 STD 42 GTS/I/O O
qb<3> 5 0 0 0 FB2_4 STD 43 I/O O
qb<4> 5 0 0 0 FB2_5 STD 40 GTS/I/O O
qa<0> 5 0 0 0 FB2_6 STD 39 GSR/I/O I/O
qa<2> 4 0 0 1 FB2_7 STD 38 I/O I/O
qa<1> 5 0 0 0 FB2_8 STD 37 I/O I/O
qa<4> 5 0 0 0 FB2_9 STD 36 I/O I/O
qa<3> 5 0 0 0 FB2_10 STD 35 I/O I/O
(unused) 0 0 0 5 FB2_11 34 I/O
(unused) 0 0 0 5 FB2_12 33 I/O
(unused) 0 0 0 5 FB2_13 29 I/O I
(unused) 0 0 0 5 FB2_14 28 I/O I
(unused) 0 0 0 5 FB2_15 27 I/O
(unused) 0 0 0 5 FB2_16 26 I/O
counter_1 2 0 0 3 FB2_17 STD 25 I/O (b)
counter_0 2 0 0 3 FB2_18 STD (b) (b)
Signals Used by Logic in Function Block
1: clk 5: "qa<0>" 8: "qa<3>"
2: counter_0 6: "qa<1>" 9: "qa<4>"
3: counter_1 7: "qa<2>" 10: right
4: counter_2
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
qb<1> XXXX.X...X.............................. 6 6
qb<0> XXXXX....X.............................. 6 6
qb<2> XXXX..X................................. 5 5
qb<3> XXXX...X.X.............................. 6 6
qb<4> XXXX....XX.............................. 6 6
qa<0> XXXXX....X.............................. 6 6
qa<2> XXXX..X................................. 5 5
qa<1> XXXX.X...X.............................. 6 6
qa<4> XXXX....XX.............................. 6 6
qa<3> XXXX...X.X.............................. 6 6
counter_1 XX...................................... 2 2
counter_0 XXXX.................................... 4 4
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
Omitting
**************************** Device Pin Out ****************************
Device : XC9536-15-PC44
q q q q q q q q q
c c c c b b b b b
< < < T < < < < < V <
0 3 2 I 4 1 0 3 2 C 4
> > > E > > > > > C >
--------------------------------
/6 5 4 3 2 1 44 43 42 41 40 \
qd<0> | 7 39 | qa<0>
qc<1> | 8 38 | qa<2>
qd<1> | 9 37 | qa<1>
GND | 10 36 | qa<4>
qd<2> | 11 XC9536-15-PC44 35 | qa<3>
qd<3> | 12 34 | TIE
qd<4> | 13 33 | TIE
TIE | 14 32 | VCC
TDI | 15 31 | GND
TMS | 16 30 | TDO
TCK | 17 29 | clk
\ 18 19 20 21 22 23 24 25 26 27 28 /
--------------------------------
q q q V q G q T T T r
e e e C e N e I I I i
< < < C < D < E E E g
1 0 2 3 4 h
> > > > > t
Legend : NC = Not Connected, unbonded pin
TIE = Tie pin to GND or board trace driven to valid logic level
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : XC9536-15-PC44
Use Timing Constraints : ON
Ignore Assignments In Design File : OFF
Create Programmable Ground Pins : OFF
Use Advanced Fitting : ON
Use Local Feedback : ON
Use Pin Feedback : ON
Default Power Setting : STD
Default Output Slew Rate : FAST
Guide File Used : NONE
Multi Level Logic Optimization : ON
Timing Optimization : ON
Power/Slew Optimization : OFF
High Fitting Effort : ON
Automatic Wire-ANDing : ON
Xor Synthesis : ON
D/T Synthesis : ON
Use Boolean Minimization : ON
Global Clock(GCK) Optimization : OFF
Global Set/Reset(GSR) Optimization : OFF
Global Output Enable(GTS) Optimization : OFF
Collapsing pterm limit : 25
Collapsing input limit : 36 |
