XACT: version D.19 Xilinx Inc.
Fitter Report
Design Name: shift_reg Date: 7-21-2000, 11:55PM
Device Used: XC9536-15-PC44
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
10 /36 ( 27%) 20 /180 ( 11%) 10 /36 ( 27%) 12 /34 ( 35%) 12 /72 ( 16%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 2 2 | I/O : 12 16
Output : 1 1 | GCK/IO : 0 3
Bidirectional : 9 9 | GTS/IO : 0 2
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 12 12
MACROCELL RESOURCES:
Total Macrocells Available 36
Registered Macrocells 10
Non-registered Macrocell driving I/O 0
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 10 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 10 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
q0 2 2 FB2_2 STD FAST 44 I/O I/O
q1 2 2 FB2_7 STD FAST 38 I/O I/O
q2 2 2 FB2_10 STD FAST 35 I/O I/O
q3 2 2 FB2_13 STD FAST 29 I/O I/O
q4 2 2 FB2_16 STD FAST 26 I/O I/O
q5 2 2 FB1_2 STD FAST 3 I/O I/O
q6 2 2 FB1_6 STD FAST 8 I/O I/O
q7 2 2 FB1_10 STD FAST 12 I/O I/O
q8 2 2 FB1_13 STD FAST 18 I/O I/O
q9 2 2 FB1_16 STD FAST 22 I/O O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
clk FB1_8 9 I/O I
din FB1_9 11 I/O I
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 5 6 6 10 1/4 17
FB2 5 6 6 10 0/5 17
---- ----- ----- -----
10 20 1/9 34
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 6/30
Number of signals used by logic mapping into function block: 6
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 2 I/O
q5 2 0 0 3 FB1_2 STD 3 I/O I/O
(unused) 0 0 0 5 FB1_3 5 GCK/I/O
(unused) 0 0 0 5 FB1_4 4 I/O
(unused) 0 0 0 5 FB1_5 6 GCK/I/O
q6 2 0 0 3 FB1_6 STD 8 I/O I/O
(unused) 0 0 0 5 FB1_7 7 GCK/I/O
(unused) 0 0 0 5 FB1_8 9 I/O I
(unused) 0 0 0 5 FB1_9 11 I/O I
q7 2 0 0 3 FB1_10 STD 12 I/O I/O
(unused) 0 0 0 5 FB1_11 13 I/O
(unused) 0 0 0 5 FB1_12 14 I/O
q8 2 0 0 3 FB1_13 STD 18 I/O I/O
(unused) 0 0 0 5 FB1_14 19 I/O
(unused) 0 0 0 5 FB1_15 20 I/O
q9 2 0 0 3 FB1_16 STD 22 I/O O
(unused) 0 0 0 5 FB1_17 24 I/O
(unused) 0 0 0 5 FB1_18 (b)
Signals Used by Logic in Function Block
1: clk 3: q5 5: q7
2: q4 4: q6 6: q8
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
q5 XX...................................... 2 2
q6 X.X..................................... 2 2
q7 X..X.................................... 2 2
q8 X...X................................... 2 2
q9 X....X.................................. 2 2
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 6/30
Number of signals used by logic mapping into function block: 6
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 1 I/O
q0 2 0 0 3 FB2_2 STD 44 I/O I/O
(unused) 0 0 0 5 FB2_3 42 GTS/I/O
(unused) 0 0 0 5 FB2_4 43 I/O
(unused) 0 0 0 5 FB2_5 40 GTS/I/O
(unused) 0 0 0 5 FB2_6 39 GSR/I/O
q1 2 0 0 3 FB2_7 STD 38 I/O I/O
(unused) 0 0 0 5 FB2_8 37 I/O
(unused) 0 0 0 5 FB2_9 36 I/O
q2 2 0 0 3 FB2_10 STD 35 I/O I/O
(unused) 0 0 0 5 FB2_11 34 I/O
(unused) 0 0 0 5 FB2_12 33 I/O
q3 2 0 0 3 FB2_13 STD 29 I/O I/O
(unused) 0 0 0 5 FB2_14 28 I/O
(unused) 0 0 0 5 FB2_15 27 I/O
q4 2 0 0 3 FB2_16 STD 26 I/O I/O
(unused) 0 0 0 5 FB2_17 25 I/O
(unused) 0 0 0 5 FB2_18 (b)
Signals Used by Logic in Function Block
1: clk 3: q0 5: q2
2: din 4: q1 6: q3
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
q0 XX...................................... 2 2
q1 X.X..................................... 2 2
q2 X..X.................................... 2 2
q3 X...X................................... 2 2
q4 X....X.................................. 2 2
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
q0 := din
q0.CLKF = clk
q0.PRLD = GND
q1 := q0.PIN
q1.CLKF = clk
q1.PRLD = GND
q2 := q1.PIN
q2.CLKF = clk
q2.PRLD = GND
q3 := q2.PIN
q3.CLKF = clk
q3.PRLD = GND
q4 := q3.PIN
q4.CLKF = clk
q4.PRLD = GND
q5 := q4.PIN
q5.CLKF = clk
q5.PRLD = GND
q6 := q5.PIN
q6.CLKF = clk
q6.PRLD = GND
q7 := q6.PIN
q7.CLKF = clk
q7.PRLD = GND
q8 := q7.PIN
q8.CLKF = clk
q8.PRLD = GND
q9 := q8.PIN
q9.CLKF = clk
q9.PRLD = GND
**************************** Device Pin Out ****************************
Device : XC9536-15-PC44
T T T T T T T V T
I I I q I I q I I C I
E E E 5 E E 0 E E C E
--------------------------------
/6 5 4 3 2 1 44 43 42 41 40 \
TIE | 7 39 | TIE
q6 | 8 38 | q1
clk | 9 37 | TIE
GND | 10 36 | TIE
din | 11 XC9536-15-PC44 35 | q2
q7 | 12 34 | TIE
TIE | 13 33 | TIE
TIE | 14 32 | VCC
TDI | 15 31 | GND
TMS | 16 30 | TDO
TCK | 17 29 | q3
\ 18 19 20 21 22 23 24 25 26 27 28 /
--------------------------------
q T T V q G T T q T T
8 I I C 9 N I I 4 I I
E E C D E E E E
Legend : NC = Not Connected, unbonded pin
TIE = Tie pin to GND or board trace driven to valid logic level
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : XC9536-15-PC44
Use Timing Constraints : ON
Ignore Assignments In Design File : OFF
Create Programmable Ground Pins : OFF
Use Advanced Fitting : ON
Use Local Feedback : ON
Use Pin Feedback : ON
Default Power Setting : STD
Default Output Slew Rate : FAST
Guide File Used : NONE
Multi Level Logic Optimization : ON
Timing Optimization : ON
Power/Slew Optimization : OFF
High Fitting Effort : ON
Automatic Wire-ANDing : ON
Xor Synthesis : ON
D/T Synthesis : ON
Use Boolean Minimization : ON
Global Clock(GCK) Optimization : OFF
Global Set/Reset(GSR) Optimization : OFF
Global Output Enable(GTS) Optimization : OFF
Collapsing pterm limit : 25
Collapsing input limit : 36 |
