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--******************************************************************************
--*                                                                            *
--*                           10 bits Shift Register                           *
--*                                                     Device : XC9536-PC44   *
--*                                                     Author : Seiichi Inoue *
--******************************************************************************

library ieee;                                    -- Defines std_logic types
use ieee.std_logic_1164.all;

entity Shift_reg is
  port ( DIN, CLK : in std_logic;                -- Defines ports
         Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9 : out std_logic);
end Shift_reg;

architecture Shift_reg_arch of Shift_reg is
  signal QIN0,QIN1,QIN2,QIN3,QIN4 : std_logic;   -- Internal signal
  signal QIN5,QIN6,QIN7,QIN8,QIN9 : std_logic;
begin
  Q0 <= QIN0;                                    -- Output data
  Q1 <= QIN1;
  Q2 <= QIN2;
  Q3 <= QIN3;
  Q4 <= QIN4;
  Q5 <= QIN5;
  Q6 <= QIN6;
  Q7 <= QIN7;
  Q8 <= QIN8;
  Q9 <= QIN9;
  process( CLK ) begin
    if CLK='1' and CLK'event then                -- Clock rising edge ?
      QIN0 <= DIN;                               -- Data shifting
      QIN1 <= QIN0;
      QIN2 <= QIN1;
      QIN3 <= QIN2;
      QIN4 <= QIN3;
      QIN5 <= QIN4;
      QIN6 <= QIN5;
      QIN7 <= QIN6;
      QIN8 <= QIN7;
      QIN9 <= QIN8;
    end if;
  end process;
end Shift_reg_arch;

--******************************************************************************
--*                        end of 10 bits Shift Register                       *
--******************************************************************************