XACT: version D.19 Xilinx Inc.
Fitter Report
Design Name: latch1 Date: 7-21-2000, 8:59PM
Device Used: XC9536-15-PC44
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
8 /36 ( 22%) 16 /180 ( 8%) 8 /36 ( 22%) 17 /34 ( 50%) 10 /72 ( 13%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 9 9 | I/O : 17 11
Output : 8 8 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 2
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 17 17
MACROCELL RESOURCES:
Total Macrocells Available 36
Registered Macrocells 8
Non-registered Macrocell driving I/O 0
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 8 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 8 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
q<0> 2 2 FB2_2 STD FAST 44 I/O O
q<1> 2 2 FB2_8 STD FAST 37 I/O O
q<2> 2 2 FB2_12 STD FAST 33 I/O O
q<3> 2 2 FB2_16 STD FAST 26 I/O O
q<4> 2 2 FB1_2 STD FAST 3 I/O O
q<5> 2 2 FB1_8 STD FAST 9 I/O O
q<6> 2 2 FB1_12 STD FAST 14 I/O O
q<7> 2 2 FB1_16 STD FAST 22 I/O O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
clk FB2_9 36 I/O I
din<0> FB2_11 34 I/O I
din<1> FB1_11 13 I/O I
din<2> FB2_7 38 I/O I
din<3> FB2_13 29 I/O I
din<4> FB1_9 11 I/O I
din<5> FB2_10 35 I/O I
din<6> FB1_6 8 I/O I
din<7> FB1_10 12 I/O I
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 4 5 5 8 4/0 17
FB2 4 5 5 8 4/0 17
---- ----- ----- -----
8 16 8/0 34
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 5/31
Number of signals used by logic mapping into function block: 5
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 2 I/O
q<4> 2 0 0 3 FB1_2 STD 3 I/O O
(unused) 0 0 0 5 FB1_3 5 GCK/I/O
(unused) 0 0 0 5 FB1_4 4 I/O
(unused) 0 0 0 5 FB1_5 6 GCK/I/O
(unused) 0 0 0 5 FB1_6 8 I/O I
(unused) 0 0 0 5 FB1_7 7 GCK/I/O
q<5> 2 0 0 3 FB1_8 STD 9 I/O O
(unused) 0 0 0 5 FB1_9 11 I/O I
(unused) 0 0 0 5 FB1_10 12 I/O I
(unused) 0 0 0 5 FB1_11 13 I/O I
q<6> 2 0 0 3 FB1_12 STD 14 I/O O
(unused) 0 0 0 5 FB1_13 18 I/O
(unused) 0 0 0 5 FB1_14 19 I/O
(unused) 0 0 0 5 FB1_15 20 I/O
q<7> 2 0 0 3 FB1_16 STD 22 I/O O
(unused) 0 0 0 5 FB1_17 24 I/O
(unused) 0 0 0 5 FB1_18 (b)
Signals Used by Logic in Function Block
1: clk 3: "din<5>" 5: "din<7>"
2: "din<4>" 4: "din<6>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
q<4> XX...................................... 2 2
q<5> X.X..................................... 2 2
q<6> X..X.................................... 2 2
q<7> X...X................................... 2 2
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 5/31
Number of signals used by logic mapping into function block: 5
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 1 I/O
q<0> 2 0 0 3 FB2_2 STD 44 I/O O
(unused) 0 0 0 5 FB2_3 42 GTS/I/O
(unused) 0 0 0 5 FB2_4 43 I/O
(unused) 0 0 0 5 FB2_5 40 GTS/I/O
(unused) 0 0 0 5 FB2_6 39 GSR/I/O
(unused) 0 0 0 5 FB2_7 38 I/O I
q<1> 2 0 0 3 FB2_8 STD 37 I/O O
(unused) 0 0 0 5 FB2_9 36 I/O I
(unused) 0 0 0 5 FB2_10 35 I/O I
(unused) 0 0 0 5 FB2_11 34 I/O I
q<2> 2 0 0 3 FB2_12 STD 33 I/O O
(unused) 0 0 0 5 FB2_13 29 I/O I
(unused) 0 0 0 5 FB2_14 28 I/O
(unused) 0 0 0 5 FB2_15 27 I/O
q<3> 2 0 0 3 FB2_16 STD 26 I/O O
(unused) 0 0 0 5 FB2_17 25 I/O
(unused) 0 0 0 5 FB2_18 (b)
Signals Used by Logic in Function Block
1: clk 3: "din<1>" 5: "din<3>"
2: "din<0>" 4: "din<2>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
q<0> XX...................................... 2 2
q<1> X.X..................................... 2 2
q<2> X..X.................................... 2 2
q<3> X...X................................... 2 2
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
"q<0>" := "din<0>"
"q<0>".CLKF = clk
"q<0>".PRLD = GND
"q<1>" := "din<1>"
"q<1>".CLKF = clk
"q<1>".PRLD = GND
"q<2>" := "din<2>"
"q<2>".CLKF = clk
"q<2>".PRLD = GND
"q<3>" := "din<3>"
"q<3>".CLKF = clk
"q<3>".PRLD = GND
"q<4>" := "din<4>"
"q<4>".CLKF = clk
"q<4>".PRLD = GND
"q<5>" := "din<5>"
"q<5>".CLKF = clk
"q<5>".PRLD = GND
"q<6>" := "din<6>"
"q<6>".CLKF = clk
"q<6>".PRLD = GND
"q<7>" := "din<7>"
"q<7>".CLKF = clk
"q<7>".PRLD = GND
**************************** Device Pin Out ****************************
Device : XC9536-15-PC44
q q
T T T < T T < T T V T
I I I 4 I I 0 I I C I
E E E > E E > E E C E
--------------------------------
/6 5 4 3 2 1 44 43 42 41 40 \
TIE | 7 39 | TIE
din<6> | 8 38 | din<2>
q<5> | 9 37 | q<1>
GND | 10 36 | clk
din<4> | 11 XC9536-15-PC44 35 | din<5>
din<7> | 12 34 | din<0>
din<1> | 13 33 | q<2>
q<6> | 14 32 | VCC
TDI | 15 31 | GND
TMS | 16 30 | TDO
TCK | 17 29 | din<3>
\ 18 19 20 21 22 23 24 25 26 27 28 /
--------------------------------
T T T V q G T T q T T
I I I C < N I I < I I
E E E C 7 D E E 3 E E
> >
Legend : NC = Not Connected, unbonded pin
TIE = Tie pin to GND or board trace driven to valid logic level
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : XC9536-15-PC44
Use Timing Constraints : ON
Ignore Assignments In Design File : OFF
Create Programmable Ground Pins : OFF
Use Advanced Fitting : ON
Use Local Feedback : ON
Use Pin Feedback : ON
Default Power Setting : STD
Default Output Slew Rate : FAST
Guide File Used : NONE
Multi Level Logic Optimization : ON
Timing Optimization : ON
Power/Slew Optimization : OFF
High Fitting Effort : ON
Automatic Wire-ANDing : ON
Xor Synthesis : ON
D/T Synthesis : ON
Use Boolean Minimization : ON
Global Clock(GCK) Optimization : OFF
Global Set/Reset(GSR) Optimization : OFF
Global Output Enable(GTS) Optimization : OFF
Collapsing pterm limit : 25
Collapsing input limit : 36 |
