[Menu]/[CPLD]/[4-16 Decoder]


Source code and Explanation
for 4-16 Decoder

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--******************************************************************************
--*                                                                            *
--*                             4 - 16 Decoder                                 *
--*                                                     Device : XC9536-PC44   *
--*                                                     Author : Seiichi Inoue *
--******************************************************************************

library ieee;                                    -- Defines std_logic types
use ieee.std_logic_1164.all;

entity Decoder2 is
  port ( A, B, C, D : in std_logic;              -- Defines ports
         Q : out std_logic_vector(15 downto 0));
end Decoder2;

architecture Decoder2_arch of Decoder2 is
  signal IN_DATA : std_logic_vector(3 downto 0); -- Defines internal signals
begin
  IN_DATA <= D & C & B & A;                      -- Binding vector
  process( IN_DATA ) begin
    case IN_DATA is                              -- Decode with input data
      when "0000" => Q <= "0000000000000001";
      when "0001" => Q <= "0000000000000010";
      when "0010" => Q <= "0000000000000100";
      when "0011" => Q <= "0000000000001000";
      when "0100" => Q <= "0000000000010000";
      when "0101" => Q <= "0000000000100000";
      when "0110" => Q <= "0000000001000000";
      when "0111" => Q <= "0000000010000000";
      when "1000" => Q <= "0000000100000000";
      when "1001" => Q <= "0000001000000000";
      when "1010" => Q <= "0000010000000000";
      when "1011" => Q <= "0000100000000000";
      when "1100" => Q <= "0001000000000000";
      when "1101" => Q <= "0010000000000000";
      when "1110" => Q <= "0100000000000000";
      when "1111" => Q <= "1000000000000000";
      when others => Q <= "XXXXXXXXXXXXXXXX";    -- Illegal condition
    end case;
  end process;
end Decoder2_arch;

--******************************************************************************
--*                            end of 4 - 16 Decoder                           *
--******************************************************************************

Explanation
Line #Comment
009The std_logic library is specified.
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-013
The pins of the input/output are specified.
017 The signal which is used by the Case sentence is defined.
It is specified by the 4-bit vector.
019The inputs are connected with the inner signal. Because the input is 1 bit respectively, they are binded using &.
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-037
It is generated in the output code with correspondence with the input code by the Case sentence.
038 All conditions must be specified by the Case sentence.
It becomes a syntax error when not specifying "when others =>" even if it specifies all conditions.
The case of "when others =>" doesn't occur. So, X(Either of 0 or 1 is OK) is mentioned to the output.