001
002
003
004
005
006
007
008
009
010
011
012
013
014
015
016
017
018
019
020
021
022
023
024
025
026
027
028
029
030
031
032
033
034
035
036
037
038
039
040
041
042
043
044
045 | --******************************************************************************
--* *
--* 4 - 16 Decoder *
--* Device : XC9536-PC44 *
--* Author : Seiichi Inoue *
--******************************************************************************
library ieee; -- Defines std_logic types
use ieee.std_logic_1164.all;
entity Decoder2 is
port ( A, B, C, D : in std_logic; -- Defines ports
Q : out std_logic_vector(15 downto 0));
end Decoder2;
architecture Decoder2_arch of Decoder2 is
signal IN_DATA : std_logic_vector(3 downto 0); -- Defines internal signals
begin
IN_DATA <= D & C & B & A; -- Binding vector
process( IN_DATA ) begin
case IN_DATA is -- Decode with input data
when "0000" => Q <= "0000000000000001";
when "0001" => Q <= "0000000000000010";
when "0010" => Q <= "0000000000000100";
when "0011" => Q <= "0000000000001000";
when "0100" => Q <= "0000000000010000";
when "0101" => Q <= "0000000000100000";
when "0110" => Q <= "0000000001000000";
when "0111" => Q <= "0000000010000000";
when "1000" => Q <= "0000000100000000";
when "1001" => Q <= "0000001000000000";
when "1010" => Q <= "0000010000000000";
when "1011" => Q <= "0000100000000000";
when "1100" => Q <= "0001000000000000";
when "1101" => Q <= "0010000000000000";
when "1110" => Q <= "0100000000000000";
when "1111" => Q <= "1000000000000000";
when others => Q <= "XXXXXXXXXXXXXXXX"; -- Illegal condition
end case;
end process;
end Decoder2_arch;
--******************************************************************************
--* end of 4 - 16 Decoder *
--****************************************************************************** |