Source code and Explanation for 5 Binary Counter

Source code and Explanation
for 5 Binary Counter

--******************************************************************************
--*                                                                            *
--*                   5 Binary Counter with Count Enable                       *
--*                                                     Device : XC9536-PC44   *
--*                                                     Author : Seiichi Inoue *
--******************************************************************************

library ieee;                                    -- Defines std_logic types
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity Counter5 is
  port ( CLK,CLEAR,CE : in std_logic;            -- Defines ports
         Q5 : out std_logic_vector(2 downto 0));
  attribute pin_assign : string;                 -- Pin Assign
  attribute pin_assign of CE : signal is "1";
  attribute pin_assign of Q5 : signal is "13,12,11";
  attribute bufg: string;
  attribute bufg of CLK : signal is "CLK";
  attribute bufg of CLEAR : signal is "SR";
end Counter5;

architecture Counter5_ARCH of Counter5 is
signal Q5_IN : std_logic_vector(2 downto 0);     -- Defines internal signals
begin
  Q5 <= Q5_IN;                                   -- Set output
  process( CLEAR, CLK, CE ) begin
    if CLEAR='0' then                            -- Clear counter ?
      Q5_IN <= "000";                            -- Yes. Clear counter
    elsif CLK='1' and CLK'event then             -- Clock rising edge ?
       if CE='1' then                            -- Yes. Count Enable ?
          if Q5_IN=4 then                        -- Yes. Count = 4 ?
             Q5_IN <= "000";                     -- Yes. Clear counter
          else                                   -- No
             Q5_IN <= Q5_IN + '1';               -- Count-up
          end if;
       end if;                                   -- Count Disable(Stop)
    end if;
  end process;
end Counter5_ARCH;

--******************************************************************************
--*                          end of 5 Binary Counter                           *
--******************************************************************************

Explanation

Line #	Comment
010	This library is needed for the calculation to be using in 036.
015	The output of the counter is specified by the 3-bit vector.
016 -018	The pins of the input/output are specified.
019 -021	The specification of the global pins(GCK and GSR) are done.
025	The counter to use by the logical operation inside is defined. This is limitation on VHDL. The object which was specified as output (OUT) can not be used inside the entity. It is specified by the 3-bit vector like the output.
027	It ties a counter for the inner calculation to the output counter.
029 030	CLEAR input is judged first. When the CLEAR input is '0' (the L level), a counter is cleared and the logic is completed.
031	When CLEAR is not 'L', this logic is executed. The judgement when clock (CLK) changes from 0 to 1(Count mode) is done. "CLK='1' and CLK'event" is the description which detects that CLK changed into '1' from '0'.
032	In case of count enable (CE=1), it advances towards count logic (033). If not so (CE=0), the logic is completed. A count isn't done.
033 034	A maximum judgment with counter value is done. Because it is a 5 binary counter(Count from 0 to 4) this time, it is judging whether or not the count value is 4. When you want to make a 6 binary counter, it makes a judgement value 5. In case of the maximum, a counter is cleared.
036	It increments the conter. After the addition, the logic is completed.