[Menu]>[CPLD]>[Up-Down Counter]


Source code and Explanation
for 4bits Binary Up-Down Counter



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--******************************************************************************
--*                                                                            *
--*      Synchronous Binary 4bits Up-Down Counter without Carry/Borrow         *
--*                                                     Device : XC9536-PC44   *
--*                                                     Author : Seiichi Inoue *
--******************************************************************************

library ieee;                                    -- Library declaration
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity UD_COUNTER1 is
  port ( CLK,CLEAR,LOAD,CE,UP : in std_logic;    -- INPUT and OUTPUT declaration
         DIN : in std_logic_vector(3 downto 0);
         Q : out std_logic_vector(3 downto 0));
  attribute pin_assign : string;                 -- Pin assign
  attribute pin_assign of CLK : signal is "1";
  attribute pin_assign of CLEAR : signal is "2";
  attribute pin_assign of LOAD : signal is "3";
  attribute pin_assign of CE : signal is "4";
  attribute pin_assign of UP : signal is "8";
  attribute pin_assign of DIN : signal is "38,37,36,35";
  attribute pin_assign of Q : signal is "14,13,12,11";
end UD_COUNTER1;

architecture UD_COUNTER_ARCH of UD_COUNTER1 is
signal Q_IN : std_logic_vector(3 downto 0);      -- Internal counter signal
begin
  Q <= Q_IN;                                     -- Set output
  process( CLEAR, CLK, LOAD, CE, UP ) begin
    if CLEAR='1' then                            -- CLEAR = ON ?
       Q_IN <= "0000";                           -- Yes. Counter clear
    elsif CLK='1' and CLK'event then             -- Clock in ?
       if LOAD='1' then                          -- Yes. LOAD = ON ?
          Q_IN <= DIN;                           -- Set Input to Output
       else                                      -- LOAD = OFF
          if CE='1' then                         -- Count Enable ?
             if UP='1' then                      -- Yes. Up count ?
                Q_IN <= Q_IN + '1';              -- Yes. Count-up
             else                                -- Not count-up
                Q_IN <= Q_IN - '1';              -- Count-down
             end if;
          end if;                                -- Not CE = 1
       end if;
    end if;
  end process;
end UD_COUNTER_ARCH;

--******************************************************************************
--*             end of Synchronous Binary 4bits Up-Down Counter                *
--******************************************************************************






Explanation
Line #Comment
010This library is needed for the calculation to be using in 039 and 041.
014The input to preset a counter is specified by the 4-bit vector.
015The output of the counter is specified by the 4-bit vector too.
016
-023		The pins of the input/output are specified.
027 The counter to use by the logical operation inside is defined.
This is limitation on VHDL. The object which was specified as output (OUT) can not be used inside the entity.
It is specified by the 4-bit vector like the output.
029It ties a counter for the inner calculation to the output counter.
031
032		 CLEAR input is judged first.
When the CLEAR input is '1' (the H level), a counter is cleared and the logic is completed.
033 When CLEAR is not '1', this logic is executed.
The judgement when clock (CLK) changes from 0 to 1(Count mode) is done.
"CLK='1' and CLK'event" is the description which detects that CLK changed into '1' from '0'.
034When the clock is a count mode, load (DOAD) input is judged.
035In case of load instruction (LOAD=1), data input (DIN) is set to the counter and the logic is completed.
036In case of not being a load instruction (LOAD=0), it advances towards 037 logic.
037 In case of count enable (CE=1), it advances towards count logic (038).
If not so (CE=0), the logic is completed. A count isn't done.
038 In case of count up instruction(UP=1), it advances towards count up logic (039).
If not so (the count-down), it advances towards count-down logic (040).
039It increments the conter. After the addition, the logic is completed.
040
041		It decrements the conter. After the subtraction, the logic is completed.