The function of the CPLD device can be made using the development language(VHDL, Verilog, ABEL ...) like the software.
To write the file(JEDEC file) which was made by using a fitting tool at the CPLD device, a connection cable is needed.
The CPLD device of the Xilinx Inc. can write data on the personal computer to the CPLD device with the JTAG protocol specified by IEEE1149.1 (JTAG Boundary Scan). Because the pins for JTAG (TMS, TCK, TDI and TDO) are provided in 9500 series of the Xilinx Inc., the data of the CPLD device which was mounted on the printed board can be rewritten. Of course, the connector for JTAG pins must be prepared.
The method of the Xilinx Inc.
In case of the tool of the Xilinx Inc., a download cable is used as the cable which connects a personal computer and a device. A cable is connected with the printer port (the parallel port) of the personal computer using the DSUB-25 connector. A cable is connected with the side of the device with the small pin. Also, the cable has the function which revises a level using bus buffer ICs(74HC125).
This time, I made CPLD programmer.
This equipment is the one to write data at the XC9500 series CPLD device of PC44 and PC84.
PLCC of 44 pins and 84 pins is mounted on the programmer. It is connected with the parallel port (the printer port) of the personal computer with the cable. The programmer has bus buffers. Moreover, the JTAG cable(Hand made) can be connected that it is possible to write at the device to have mounted on the printed board, too.
Also, I connect all pins with the terminal to be able to do operation confirmation after programming.
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